In large computers such as scientific processors, stored program instructions are read into an instruction buffer. Instructions are fetched from the instruction buffer in response to a signal from a program address generator. The fetched instructions are applied to an instruction translate RAM which reads bits of pre-issue instruction decode information. Hold registers typically hold instructions just fetched from the instruction buffer until those instructions are mapped in the translate RAM and transferred into the instruction registers and decoder. An address into the translate RAM is the Operation Code of the instruction which allocates one location for the translation of each Operation Code.
Conventional instruction translate logic is a mass of interconnected complicated logic requiring many chips for the purpose of accomplishing pre-issue instruction decode. This arrangement typically causes many problems related to space requirements, cooling, power, interconnect limitations, performance and expense.
The foregoing illustrates limitations known to exist in present devices. Thus, it is apparent that it would be advantageous to provide an alternative directed to overcoming one or more of the limitations set forth above. Accordingly, a suitable alternative is provided including features more fully disclosed hereinafter.